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Microcontrollers ApNote AP163702
Reset and System Startup Configuration via PORT0
This application note presents an overview about the different reset types and the behaviour concerning the system startup configuration via PORT0. The calculation for the Pull-up/down resistors at PORT0 is also included.
Author: Mariutti / HL DC AT
Semiconductor Group
6.98, Rel 02
Reset and System Startup
Contents 1 1.1 1.2 1.3 1.4 2 2.1 2.2 3 3.1 3.2 4 A B
Page 3 3 4 4 4
Overview about the different Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bidirectional Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Startup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Overview about PORT0 Configuration during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PORT0 Sample Timing for the different Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Calculation of the Pull-up/down Resistors at PORT0 for Startup Configuration . . 10 Pull-down Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pull-up Calculation at Port_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PORT0 Configuration during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock Options and Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AP163702 ApNote - Revision History Actual Revision : 6.98 Previous Revision : 9.97 Page of actual Rev. 4 5 6 11 14 15 Page of prev.Rel. 4 5 6 11 14 15 Subjects (changes since last release) 1.4 Bidirectional Reset: Device list updated 'IO line' replaced by 'IO line with an integrated pull-up resistor' Table 2: Column EA and RD added Figure 9: Sign of ISY S H corrected Order of CSSEL pins corrected Appendix clock options and steps updated
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1
Overview about the different Reset Sources
During reset, the device executes a special internal sequence in order to set inside signals and the special function registers to their specified default values. The contents of some special function registers are controlled during system startup configuration via PORT0. The system startup configuration is sampled upon different reset events. See table 1: i Hardware Reset: - Power-on Reset - Short Hardware Reset (Warm Reset) - Long Hardware Reset (Power Down Wakeup Reset)
i Software Reset i Watchdog Timer Reset
Reset Source Power-on Reset Short Hardware Reset Long Hardware Reset Watchdog Timer Reset Software Reset Table 1: Reset Sources and Reset Conditions
Short-cut PONR SHWR LHWR WDTR SWR
Condition Power-on 4 TCL < tRSTIN 1024 TCL tRSTIN > 1024 TCL WDT overflow SRST command
1.1
Hardware Reset
A hardware reset is triggered when the reset input signal RSTIN is latched low. To ensure the recognition of the RSTIN signal (latching), it must be held low for at least 2 CPU clock cycles (4 TCL = 100 nsec @ 20 MHz CPU Clock). Also shorter RSTIN pulses may trigger a hardware reset, if they coincide with the latch's sample point. However, for microcontrollers with an on-chip PLL it is recommended to keep RSTIN low for ca. 1 msec to guarantee that the PLL is locked. After the reset sequence has been completed, the RSTIN input is sampled. When the reset input signal is active at that time the internal reset condition is prolonged until RSTIN gets inactive. The input RSTIN provides an internal pullup device equalling a resistor of 50 K to 150 K (the minimum reset time must be determined by the lowest value). Simply connecting an external capacitor is sufficient for an automatic power-on reset. RSTIN may also be connected to the output of other logic gates.
Three different kinds of external hardware resets have to be considered: a) Power-on Reset A complete power-on reset requires an active RSTIN time of two reset sequences (2 * 1024 TCL = 51.2 sec @ 20 MHz CPU Clock) after a stable clock signal is available.
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Depending on the oscillation frequency the on-chip oscillator needs about 2...50 ms to stabilize. b) Long Hardware Reset A long hardware reset requires an active RSTIN time longer than the duration of the internal reset sequence. The duration of the internal reset sequence is 1024 TCL (1024 TCL = 25.6 sec @ 20 MHz CPU Clock). The long hardware reset is also named power down wakeup reset. c) Short Hardware Reset The active RSTIN time of a short hardware reset is between 4 TCL and 1024 TCL. If the RSTIN signal is active for at least 4 TCL clock cycles (100 nsec @ 20 MHz CPU Clock) the internal reset sequence is started (1024 TCL, 25.6 sec @ 20 MHz CPU Clock). After the internal reset sequence has been completed, the RSTIN input is sampled. When the reset input is still active at that time the internal reset condition is prolonged until RSTIN gets inactive. If the RSTIN signal is active for more then 1024 TCL then the behaviour of the PORT0 latch mechanism is equal to a long hardware reset.
1.2
Software Reset
The reset sequence can be triggered at any time via the protected instruction SRST (Software Reset). This instruction can be executed deliberately within a program, e.g. to leave bootstrap loader mode, or upon a hardware trap that reveals a system failure.
1.3
Watchdog Timer Reset
When the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence. The watchdog timer reset releases automatically a software reset. Other than a hardware reset the watchdog timer reset completes a running external bus cycle if this bus cycle either does not use READY at all, or if READY is sampled active (low) after the programmed waitstates. When READY is sampled inactive (high) after the programmed waitstates the running external bus cycle is aborted. Then the internal reset sequence is started. Note: The watchdog timer reset cannot occur while the device is in bootstrap loader mode! 1.4 Bidirectional Reset
The bidirectional reset is a new feature and implemented since the devices and steps listed below. The steps in parentheses do only reflect a software- or watchdog timer Reset to RSTIN but not a short hardware reset as shown in figure 7. C161RI AA - Step C161CI AA - Step C164CI-8EM AA - Step C167CS-32FM AA - Step C167CR-LM (CA), CB - Step C167S-4RM (BA), BB - Step C167CR-4RM (AB), AC - Step
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In bidirectional reset mode the device's line RSTIN (normally an input) may be driven active by the chip logic e.g. in order to support external equipment which is required for startup (e.g. flash memory).
RSTIN
Internal Circuitry
Reset sequence active BDRSTEN = '1'
&
Figure 1 : Bidirectional Reset Operation
Bidirectional reset reflects internal reset sources (software, watchdog) also to the RSTIN pin and converts short hardware reset pulses to a minimum duration of the internal reset sequence. Bidirectional reset is enabled by setting bit BDRSTEN in register SYSCON (SYSCON.3) and changes RSTIN from a pure input to an open drain IO line with an integrated pull-up resistor. When an internal reset is triggered by the SRST instruction or by a watchdog timer overflow or a low level is applied to the RSTIN line, an internal driver pulls it low for the duration of the internal reset sequence. After that it is released and is then controlled by the external circuitry alone. The bidirectional reset function is useful in applications where external devices require a defined reset signal but cannot be connected to the device's RSTOUT signal, e.g. an external flash memory which must come out of reset and deliver code well before RSTOUT can be deactivated via EINIT. The following behaviour differences must be observed when using the bidirectional reset feature in an application:
i Bit BDRSTEN in register SYSCON cannot be changed after EINIT. i After a reset bit BDRSTEN is cleared (bidirectional reset is disabled). i Bit WDTR will always be '0', even after a watchdog timer reset. i The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap
loader maybe activated when P0L.4 is low. i Pin RSTIN may only be connected to external reset devices with an open drain output driver.
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2
System Startup Configuration
Some system features have to be selected before the first program execution is performed. These selections are made during reset via the Pins of PORT0, which are latched at the end of reset.
2.1
Overview about PORT0 Configuration during Reset
PORT0 startup configuration is sampled either with the end of the internal reset sequence or with the end of the external hardware reset. If the external RSTIN signal is deactivated before the end of the internal reset sequence (short hardware reset) then an internal reset signal (IRS) of the device is used to latch the system startup configuration at PORT0, else (power-on reset or long hardware reset) PORT0 is latched after the rising edge of RSTIN with the IRS. The sampling point of PORT0 is 7 TCL (prescaler enabled) or 10 TCL (direct drive or PLL) after the rising edge of RSTIN as shown in the PORT0 sample timing (see figures below). The duration of one internal reset sequence is 1024 TCL for initializing the internal special function registers plus 10 TCL for the jump to address 00'0000 H after the internal reset sequence. As already mentioned the bidirectional reset feature converts software reset, WDT reset or short hardware reset to an externally visible hardware reset with a duration of 1024 TCL. This feature is disabled after hardware reset and can be enabled via software.
X:
Pin is sampled
PORT0 Emu Mode Invert P0H.7 Ext. Access Enable P0L.0 EA X --X (OWD disable) RD X X X X X X Adapt Mode P0L.1 WR Config. Addr. Lines
Reserved
Reserved P0L.3 X X X X X
BDRST
Selects
Clock options
Segm.
Type
-:
Pin is not transparent and not sampled
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0L.7
P0L.6
P0L.5
P0L.4
Sample event PONR LHWR SHWR WDTR/SWR SHWR WDTR/SWR OFF
ON/OFF
X X X X
X X X X
X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X
X X X X X
P0L.2 X X X X X
-
P0H.0
Reserved
Chip
BSL
Bus
X XXX X XXX X X-
OFF OFF ON ON
X XXX X XXX
Table 2: System Startup Configuration via PORT0
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2.2
PORT0 Sample Timing for the different Reset Types
The different reset sources and timing relations at PORT0 during and at the end of reset are shown below. If a reset event occurs then PORT0 is switched to input mode and the internal pull-ups are active. During that time it is possible that the desired input voltage levels at PORT0 (V IH and VIL forced by the internal/external pull-ups and pull-downs for the startup configuration) are not reached. Therefore PORT0 is not transparent for 1024TCL (power-on reset for 2048 TCL) to prevent unexpected behaviour to the system. After that time a part of PORT0 becomes transparent and at the end of reset these pins are sampled with the IRS signal. Depending on the reset type some PORT0 pins are not transparent, e.g. P0L.1 and P0L.0 which control Adapt Mode and Emulation Mode. Noise on these lines during reset would force the microcontroller to Adapt Mode or Emulation Mode. Therefore both pins are not transparent until the sample point IRS at the end of the reset condition. The PORT0 sample timings shown below are based on the following conditions: tP0fix: tSHR: IRS: During tP0fix PORT0 has to be constant so the System Startup Configuration is latched correctly. Duration of a short hardware reset. 4 TCL < tSHR 1024 TCL Internal Reset Signal: Sampling point of PORT0 configuration bits is 7 TCL (prescaler enabled) or 10 TCL (direct drive or PLL) after the rising edge of RSTIN or after the end of the internal reset sequence. 1 TCL = 1 / (2 *fCPU), 1 TCL = 25 nsec @ 20 MHz CPU Clock
TCL:
2048 TCL RSTIN P0[15:2] P0[1:0] System clock available Figure 2 : PORT0 sample Timing: Power-on Reset not transparent transparent not transparent tP0fix
12 TCL
IRS
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1024 TCL RSTIN P0[15:2] P0[1:0] not transparent transparent not transparent tP0fix
12 TCL
IRS Figure 3 : PORT0 sample Timing: Long Hardware Reset, Bidirectional Reset enabled or disabled
tSHR RSTIN P0[12:2] P0[15:13] P0[1:0] not transparent not transparent not transparent 1024 TCL
12 TCL
transp.
tP0fix IRS
Figure 4 : PORT0 sample Timing: Short Hardware Reset, Bidirectional Reset disabled
12 TCL 1024 TCL P0[12:6] not transparent tP0fix transp.
P0[15:13] P0[5:0] SW- or WDT Reset
not transparent IRS
Figure 5 : PORT0 sample Timing: Software Reset or WDT Reset, Bidirectional Reset disabled
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1024 TCL RSTIN P0[15:2] P0[1:0] SW- or WDT Reset not transparent transparent not transparent tP0fix
12 TCL
IRS
Figure 6 : PORT0 sample Timing: Software Reset and WDT Reset, Bidirectional Reset enabled
1024 TCL RSTIN P0[15:2] P0[1:0] not transparent not transparent tP0fix transparent
12 TCL
IRS Figure 7 : PORT0 sample Timing: Short Hardware Reset, Bidirectional Reset enabled
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3
Calculation of the Pull-up/down Resistors at PORT0 for Startup Configuration
The specification in the Data Sheet includes the values of the PORT0 configuration currents I P0L and IP0H. 3.1 Pull-down Calculation
IP0L is the base for the calculation of the Pull-down resistors for PORT0 startup configuration. IP0Lmin = -100 A @ VIN = VILmax. That means that the port configuration current has to be more or equal than 100 A to get an input voltage VIN lower or equal to VILmax. The system current ISYSL has a direct influence on the value of the needed pull-down resistor. The relation between the different parameters and the calculation with an example are shown below. Note: All currents flowing into the microcontroller are defined as positive and all currents flowing out of it are defined as negative. Because of the internal pull-up transistor the direction of IP0L and IP0 H is out of the device and therefore the sign in the current specification is negative.
Vcc RESET IP0 L 100A Port 0 VIN VILmax IPD RPD ISY S L leakage current
C16x
System
Figure 8 : System Environment and Pull-down Resistor for Startup Current Specification in the Data Sheet: Vcc = 5V 10% 4.5V Vcc 5.5V 0.8V VIL m a x 1.0V IP0L |-100A|
VIL m a x = 0.2Vcc - 0.1V IP0Lmin = -100A
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Pull-down resistor calculation:
V ILmax V ILmax R PD < ------------------------ = -------------------------------------I PD I P0L + I SYSL
Example without system current: (ISYSL = 0 A) The recommended maximum value:
V ILmax 0.8 V R PD < ------------------------ = ----------------I PD 100A
RP D = 8 k
3.2
Pull-up Calculation
IP0H is the base for the calculation of the pull-up resistors for PORT0 startup configuration. IP0Hmax = -10 A @ VIN = VIHmin. As already mentioned PORT0 supplies internal pull-up resistors which are only active during Reset, or during Hold-or Adapt-mode. For normal systems this internal pull-up resistors are sufficient to reach the input high voltages at the PORT0 pins. This situation changes when the system current ISYSH exceeds 10 A. Then additional external pull-up resistors are mandatory. For example system flash memory with a high leakage current can cause an increased ISYSH. The calculation and an example are shown below.
Vcc Vcc RESET VPU IP0 H 10A Port 0 VIN VIHmin RPU
IPU - ISY S H
leakage current
C16x
System
Figure 9 : System Environment and Pull-up Resistor for Startup
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Current Specification in the Data Sheet: Vcc VIH mi n = 5 V 10 % = 0.2 Vcc + 0.9 V 4.5 V 1.8 V IP0H Vcc VIH m i n |-10 A| 5.5 V 2.0 V
IP0Hmax = -10 A
Pull-up resistor calculation:
V PU V CCmin - V IHmin R PU < ------------ = --------------------------------------------------I PU I SYSH - I P0H
Example: ISYSH = 50A:
4.5 V - 1.8 V R PU < ----------------------------------- = 67.5 k 50A - 10A
The recommended maximum value: RP U = 67.5 k
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4 A
Appendix PORT0 Configuration during Reset
H.7
H.6 CLKCFG
H.5
H.4
H.3
H.2
H.1
H.0 WRC
L.7
L.6
L.5
L.4
L.3
L.2
L.1
L.0
SALSEL
CSSEL
BUSTYP
SMOD
ADP EMU
Pin EMU ADP SMOD (P0L.5:2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Mode Emulation Mode Adapt Mode Special Modes Reserved Reserved Reserved Reserved Reserved Reserved Reserved External Host Mode (EHM)1) Reserved Reserved Bootstrap Loader + CPU Host Mode1) Bootstrap Loader Reserved Reserved CPU Host Mode (CHM)1) Normal Start
Comment Condition for EHM and Quality of P0H.7 is inverted
Do not use this combination Do not use this combination Do not use this combination Do not use this combination Do not use this combination Do not use this combination Do not use this combination Requires Emulation Mode Do not use this combination Do not use this combination Serial OTP programming via BSL Start from internal boot ROM Do not use this combination Do not use this combination CPU programming mode for OTP Normal start as defined by EA pin
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BUSTYP (P0L.7:6) 00 01 10 11 WRC CSSEL (P0H.2:1) 11 10 01 00 SALSEL (P0H.4:3) 11 10 01 00 CLKCFG (P0H.7-5) 111 110 101 100 011 010 001 000
1)
External Data Bus Width 8-bit Data 8-bit Data 16-bit Data 16-bit Data Write Configuration Chip Select Lines Max: CSx...CS0 None Two: CS1...CS0 Three: CS2...CS0 Segment Address Lines Two: A17...A16 Axx...A16 None Four: A19...A16 CPU Frequency fCPU = fXTAL * F fXTAL * 4 fXTAL * 3 fXTAL * 2 fXTAL * 5 fXTAL * 1 fXTAL * 1.5 fXTAL / 2 fXTAL * 2.5
External Address Bus Mode Demultiplexed Addresses Multiplexed Addresses Demultiplexed Addresses Multiplexed Addresses
Default without pull-downs Port 6 pins free for IO
Directly accessible Address Space 256 KByte (Default, without pull-downs) (Maximum) 64 KByte (Minimum) 1 MByte Notes2) Default configuration
Direct drive
Prescaler
This modes are only valid for C161CI, C164CI and C167CS B and the User's Manuals for detailed information.
2) The clock configuration bits are not fully decoded in all devices and steps. Please use Appendix
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B
Clock Options and Steps
Device SAx-C161V / K / O SAx-C161RI SAx-C161SI / CI SAx-C163 SAx-C163-16F SAx-C163-16F x SAx-C164CI SAx-C165 SAx-C165 SAx-C167-LM SAx-C167SR-LM SAx-C167SR-LM SAx-C167SR-LM SAx-C167CR-LM SAx-C167CR-LM SAx-C167S-4RM SAx-C167CR-4RM SAx-C167CR-16RM SAx-C167CR-16FM SAx-C167CS-32FM
Step1) AA AA, BA, BB AA AA, AB, BA, BB AA, AB BA, BB AA BB CA BA, BB, CA, CB, BE AB BA
OWD2) == == RD
VPP/OWE VPP/OWE
PM3) Clock Options 4) PLL Factors (F) no yes yes no no no yes no no no no no no no no no no no no yes 0.5 / 1 0.5 / 1 0.5 / 1 / PLL 0.5 / 1 / PLL 0.5 / 1 / PLL 0.5 / 1 / PLL 0.5 / 1 / PLL 0.5 0.5 / 1 0.5 1 / PLL 1 / PLL 0.5 / 1 / PLL 1 / PLL 1 / PLL 1 / PLL 0.5 / 1 / PLL 1 / PLL 1 / PLL 0.5 / 1 / PLL no no 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 no no no 4 2/3/4/5 1.5/2/2.5/3/4/5 4 2/3/4/5 2/3/4/5 1.5/2/2.5/3/4/5 2/3/4/5 4 1.5/2/2.5/3/4/5
== RD == == == == == ==
AB BA, BB, CA, CB, BE AA,BA, BB AA, AB, AC AA AC AA
== == VPP VPP == == RD
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1)
The described options are implemented since the steps listed below.
2)
The Oscillator Watchdog (OWD) can be disabled in different kinds. : No OWD implemented.
==
VPP/OWE : A low level on pin VPP/OWE disables the OWD. RD VPP : A low level on pin RD at the end of any type of reset disables the OWD. The level of RD is latched with the IRS. See figure 2 to figure 7. : A low level on pin VPP disables the OWD.
3)
Besides other features the Power Management (PM) includes the Slow Down Devider. A separate clock path can be selected for Slow Down operation bypassing the basic clock path used for standard operation. The programmable Slow Down Devider devides the oscillator frequency by a factor of 1 ... 32.
4)
Prescaler option : 0.5 Direct drive option : 1 The PLL clock is not used for prescaler option (f CPU = fOSC * 0.5) and direct drive option (fCPU = fOSC * 1.0).
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